A two days Value added course on “VLSI Circuits and Design” was conducted on July 28-29, 2017 at Shambhavi seminar hall. The objective of this value added course was to introduce VLSI fabrication processes, design rules and design tools to the students. On first day, Mr. Raghavendra Prabhu, Asst. Professor, Department of E&E Engineering, gave insight of VLSI design flow and explained about nMOS and CMOS fabrication process. Later, students had hands on sessions with Microwind Lite where they drawn layouts of nMOS, pMOS and Transmission gates on Microwind. Students also learned how to draw the schematics in DSCH tool and then generate Verilog files. The Verilog code was then compiled in Microwind to auto generate the Layout of the schematic circuit. They also got expose of DRC and verification. For the second day, resource persons were Mr. Rathnakar Bhat and Mr. Riyaz Ahmed, Analog Design Engineers, Karmic, Manipal. They explained the design process and how the schematic and physical layout are verified. Students underwent practical sessions with Glade software. They first drawn schematic of CMOS inverter and then did layout of CMOS. They used the software to verify the consistency of layout with the schematic by using Glade software. Ms. Natasha Pais, participant of this workshop presented vote of thanks and Mr. Raghavendra Prabhu, coordinator of the workshop handed over mementos to resource persons. The workshop was successful as the students received knowledge about the VLSI. 27 students of EEE together with 4 students of ECE attended the workshop and got benefited.